1. Field of the Invention
The present invention relates to a semiconductor integrated circuit on which memory macros are mounted. In particular, the present invention relates to a technique for improving the yield of semiconductor integrated circuits and reducing the area of a fuse part by letting a plurality of memory macros share a memory macro for repair when a large number of memory macros are mounted on a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, it is common to form memories into a macro cell and mount the macro cell on a semiconductor integrated circuit such as a system LSI. When mounting memory macros, a memory cell for redundancy repair is stored inside a memory macro beforehand so that defects in a production stage are repaired at the time of probe inspection in order to improve the production yield of system LSIs.
When a memory cell for redundancy repair is stored inside a memory macro so as to perform redundancy repair, the area efficiency is poor, and a large number of redundancy repair cells are not used for repair, so that the repair efficiency is poor. Moreover, fuse parts for redundancy repair hinder wiring so that the wiring becomes complicated. When redundancy repair is introduced into a large number of mounted SRAM macros, the above-described problem is serious. Therefore, the number of circuits that can be produced per wafer is reduced, thus leading to a high production cost.